1. Field of the Invention
The present invention relates to electrically programmable and erasable nonvolatile memory, and more particularly to charge trapping memory with a bias arrangement that reads the contents of different positions in the charge trapping structure of the memory cell with great sensitivity.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Various memory cell structures based on charge trapping dielectric layers include structures known by the industry names PHINES, NROM, and SONOS, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As more net negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from, or adding positive charge to, the charge trapping layer.
Conventional memory cell structures rely on the reverse read operation to determine the contents of the memory structure. However, the reverse read technique effectively couples together multiple locations of the charge trapping structure, even when only a portion of the charge trapping structure contains data of interest. This dependence constrains the utility of using the charge trapping structure as nonvolatile memory, by narrowing the sensing window of currents measured from the reverse read technique. Less data are stored in the charge trapping structure than otherwise possible.
Power consumption is another area of potential improvement. Portable electronic devices such as music players, cell phones, and wireless devices, have a limited source of power available. The reverse read operation is a source of power drain contributing to power consumption. Similarly, such power consumption occurs in read operations that rely on contrasting levels of lateral current flow through a channel formed in the memory cell.
Thus, a need exists for a nonvolatile memory cell that can be read without suffering substantial coupling between multiple locations of the charge storage structure, even when only a portion of the charge storage structure contains data of interest. Alternately, a need exists for a read operation that reduces power consumption, compared to the reverse read operation.